1. Field of the Invention
This invention relates to electronic circuits and more specifically to the functional testing of microprocessors.
2. Description of the Relevant Art
A microprocessor is a complex electronic circuit formed upon a single monolithic semiconductor substrate which executes instructions from a predefined set of instructions. A microprocessor includes interconnected electronic devices (e.g., transistors, resistors, capacitors, and wires) which work together to fetch instructions and data from a main memory unit external to the microprocessor and operate upon the data according to the instructions. The result produced by instruction execution may be stored in the memory unit or sent to a peripheral device coupled to the microprocessor.
Electronic devices which work together to perform a specific function may be grouped together into a subsystem. One or more subsystems which work together to perform a single function may be grouped together into systems (i.e., functional units). The functional units of a microprocessor work together to fetch instructions and data from the main memory unit, and to operate upon the data according to the fetched instructions.
A new microprocessor must offer improved performance over similar existing products in order to be successful in the marketplace. One measure of microprocessor performance is the number of instructions a microprocessor can execute in a given amount of time. One way to increase the performance of a microprocessor is to simply add one or more performance-enhancing "features" to an existing architecture. As defined herein, a "feature" of a microprocessor is a functional unit or subsystem which increases the performance of the microprocessor, and does not contribute directly to any result produced by instruction execution. Thus if a given feature is not present, or is somehow rendered inoperable, the microprocessor remains able to fetch and execute instructions. The result produced by the microprocessor is the same result produced if the feature were present and operable. The amount of time required by the microprocessor to produce the result, however, is increased (i.e., the performance of the microprocessor is reduced). For example, modern microprocessors operate upon data according to an instruction in much less time than it takes to fetch the data from the main memory unit. Thus the performance of the microprocessor may be increased by reducing the number of delays during which needed instructions and data are being fetched from the main memory unit. Many common performance-enhancing features are temporary storage locations for instructions and data which may be accessed quickly, including instruction prefetch buffers, cache memory systems, and write buffers. Other performance-enhancing features include translation look-aside buffer (TLB) subsystems within cache memory systems, additional internal buses to transfer information between microprocessor functional units, and improved bus arbitration mechanisms to increase the efficiencies of the internal buses.
A cache memory system includes a relatively small number of storage locations which can be accessed very quickly. A cache memory system is typically coupled between a bus interface unit and an execution unit of the microprocessor. The bus interface unit is coupled to the main memory unit. The bus interface unit fetches needed quantities from and stores data to the main memory unit, and the execution unit performs instruction execution. The cache memory system stores instructions or data which have been recently used, or have a high probability of being required in the near future, making them readily available to the execution unit. A typical cache memory system is organized internally as several cache "lines," each of which is several bytes in length. When a needed instruction or datum (i.e., a needed quantity) is not found in the cache memory system, the bus interface unit fetches a number of bytes corresponding to the length of a cache line and including the needed quantity from the main memory unit. The entire cache line is stored in the cache memory system. The overall performance of the microprocessor is improved when needed quantities are often found within the cache memory system, eliminating the need for time-consuming accesses to the main memory unit.
An instruction prefetch buffer is a holding area for instructions which follow the instruction currently being executed by the execution unit. The instruction prefetch buffer includes a relatively small number of storage locations, and is coupled between the bus interface unit and the execution unit. If a microprocessor includes a cache memory system, the instruction prefetch buffer is typically coupled between the cache memory system and the execution system. The amount of time required to fetch an instruction from the instruction prefetch buffer is much less than the time required to obtain the instruction from either the cache memory system or the main memory unit. When instructions following the current instruction are not present within the cache memory system, the bus interface unit fetches the instructions from the main memory unit in advance of their being needed by the execution unit. Without an instruction prefetch buffer, or if the instruction prefetch buffer were somehow made inoperable, relatively long delays would be incurred following the completion of the execution of each instruction while the microprocessor fetches the next instruction from the cache memory system or the main memory unit. Thus the presence of the prefetch buffer improves the performance of the microprocessor by reducing delays incurred in the fetching of needed instructions.
A write buffer includes a relatively small number of storage locations for storing execution results waiting to be written to the main memory unit. Without a write buffer, the microprocessor must wait until time-consuming write operations which store data within the main memory unit are completed before continuing with instruction execution. The write buffer allows temporary storage of pending stores (i.e., writes) to the main memory unit. The pending writes are completed when the microprocessor is not obtaining needed instructions or data from the main memory. With a write buffer, the microprocessor is able to continue with instruction execution in a much shorter period of time following writes to the main memory unit. The presence of the write buffer thus improves the performance of the microprocessor by reducing delays incurred during writes to the main memory unit.
Modern microprocessors support a memory management technique called paging. Paging allows access to a physical address space which may be larger than the number of storage locations within the main memory unit. Paging divides the physical address space into smaller units called pages. Only pages which contain the most recently used instructions and data are stored within the main memory unit. The remaining pages are stored in a mass storage unit external to the main memory unit (e.g., a disk drive).
In order to adequately support paging, a cache memory systems typically include TLBs. Paging support typically requires information from two different tables stored within the main memory unit (i.e., a page directory and a page table). Values stored within the page directory and the page table are used to determine the physical address of a memory location. The physical address of a memory location is also required to access information within the cache memory system. A TLB, itself a cache memory system, stores the most recently used page table entries. The amount of time required to access a page table entry in a TLB is much less than the time required to obtain the page table entry from the main memory unit. Overall microprocessor performance is increased since the page table entries are often found in the readily accessible TLB, thereby reducing the required number of time-consuming accesses to the main memory unit.
Although the operations of performance-enhancing features should affect only the overall performance of the microprocessor, it is possible for a design error or a manufacturing defect within a performance-enhancing feature to cause a microprocessor to fail to produce a correct program result. Such an error may be present in the electronic devices (i.e., the hardware) which make up the feature, or within the control circuitry of the feature. For example, an error in the hardware of an instruction prefetch buffer, a cache memory system, or a write buffer, may cause the feature to introduce an error into quantities stored therein, thereby causing the microprocessor to produce an incorrect result. In addition, an error in the hardware or control circuitry of an instruction prefetch buffer may cause the buffer to provide instructions out of the intended program sequence, thereby causing the microprocessor to produce an incorrect result. An error in the hardware or control circuitry of a write buffer may cause a stored quantity to be saved in the wrong storage location within the main memory unit, thereby causing the microprocessor to produce an incorrect result.
Functional testing is typically performed to ensure a given microprocessor operates correctly. Such functional testing typically includes placing the microprocessor under test in a known internal state, applying known input signals, and comparing the response of the microprocessor to a predetermined "correct" response (i.e., an expected response). The expected response is typically derived from a list of functional requirements of the microprocessor (i.e., a functional specification of the microprocessor). Any deviation of the microprocessor response from the expected response represents a failure of the functional test.
Performance-enhancing features are tested using a technique called "intrusive testing". Intrusive testing is also used to test logic that detects the presence of outdated (i.e., "stale") information within the cache memory system, logic that arbitrates for control of the internal buses, and the synchronization between the functional units of a microprocessor. A given performance-enhancing feature typically operates according to one of several predefined methods of operation (i.e., in one of several different operating modes) as determined by the states of one or more control signals. Intrusive testing typically involves placing the feature under test into a desired operating mode, then causing the microprocessor to execute a testing program which requires operation of the feature and produces a result. Any difference between the result produced by the microprocessor and the expected result may be due to an error or defect within the hardware or control circuitry of the feature.
An intrusive testing program, executed by the microprocessor under test during the intrusive test, consists of two parts. A first part of the testing program includes software instructions which initiate the desired operating mode of the feature. A second part of the testing program includes software instructions which require operation of the feature and produce a result. The result produced by the microprocessor may then be compared to the expected result.
A significant amount of the total intrusive test generation effort is expended in writing the first part of the testing program which initiates the desired operating mode of the feature. The highly complex nature of modern microprocessors and the large amounts of data manipulation involved make generation of the first part of the testing program both cumbersome and error prone. An undiscovered error in the first part of the testing program may fail to place the selected feature in the desired operating mode. As a result, the entire intrusive test is flawed. The faulty test will fail to accomplish its goal. Furthermore, the result obtained by executing the test may erroneously indicate that the feature is or is not functioning correctly. An additional problem is created when the internal logic of a microprocessor is revised or changed. In this case, a testing program which functioned correctly prior to the logic modification may fail to initiate the desired operating mode of the feature.
It would thus be desirable to have an intrusive test methodology for architectural feature verification which decouples the task of initiating the desired operating mode of a feature under test from the task of verifying proper feature operation, and also simplifies the task of initiating the desired operating mode of the feature being selected.